张钊，男，博士，研究员，博士生导师。
1989年出生，2011年获北京邮电大学工学学士学位，2016年毕业于中国科学院半导体研究所，获中国科学院大学工学博士学位；2016-2018年在香港科技大学电子及计算机工程学系从事博士后研究；2019-2020年任日本广岛大学的助理教授。2020年底进入半导体所超晶格国家重点实验室工作至今。
从事高性能数模混合集成电路及系统的设计技术研究，共发表学术论文40余篇。以第一作者身份（部分兼通讯作者）发表学术论文28篇，包括：集成电路设计顶级期刊IEEE Journal of Solid-State Circuits (JSSC)、电路与系统领域顶级期刊IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)和IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)、集成电路设计高水平期刊IEEE Transactions on Very Large Scale Integration Systems (TVLSI)、集成电路设计顶级会议IEEE International Solid-State Circuits Conference (ISSCC)和Symposium on VLSI Circuits (VLSI)、集成电路设计高水平会议IEEE Asian Solid-State Circuits Conference (A-SSCC)等。
担任国际会议2018 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2018) 的分会主席，2020 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2020) 的分会主席。自2020 年起担任国际会议IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2020 & 2021)技术程序委员会委员。此外，还担任JSSC、TCAS-I、TCAS-II、TMTT等IEEE权威SCI期刊的审稿人。
主要研究领域方向：
1. 高性能时钟生成集成电路（PLL, DLL, Frequency Synthesizer, 多相时钟生成及分布电路等）
2. 高速有线通信集成电路设计（SerDes，均衡补偿，光电接口等）
3. 极低电压极低功耗集成电路设计（面向自供电传感器节点应用，包括IoT、生物医疗等）
取得的重要科研成果：
1. 高性能时钟生成器集成电路设计：2017年研制出一款频率为18-23 GHz，RMS抖动小于60 fs，功耗13.7 mW的低功耗极低抖动锁相环时钟生成器，优值系数-253.5 dB，该项成果发表在电路与系统领域旗舰期刊IEEE Transactions on Circuits and Systems I: Regular Papers；2019年研制出一款能够在0.65-V电源电压下工作且RMS抖动小于60 fs的低功耗极低抖动抖动锁相环芯片，首次将小于60 fs的极低抖动锁相环的电源电压与功耗分别降低至0.7 V和8 mW以内，该项成果分表在集成电路设计的顶级会议ISSCC 2019 (IEEE International Solid-State Circuits Conference)和顶级期刊JSSC 2020 (IEEE Journal of Solid-State Circuits)上。
2. 用于数据中心的高速有线通信集成电路设计：2019分别研制出一款能效为 0.92 pJ/bit的52-Gb/s PAM4 Receiver，在速率超过50 Gb/s前提下，能效首次优于1 pJ/bit，该项成果发表在集成电路设计顶级会议VLSI 2019 (2019 Symposia on VLSI Circuits)；2020年研制出能效和恢复时钟抖动分别小于0.5 pJ/bit和360 fs的低功耗低抖动32-Gb/s PAM4 CDR，该项成果作发表在集成电路设计顶级期刊JSSC 2020 (IEEE Journal of Solid-State Circuits)上；2021年研制出具有抖动补偿消除功能的60-Gb/s PAM4 Receiver，首次打破PAM4 CDR中抖动传递（JTRAN）和抖动容限（JTOL）之间的折中关系，能够在获得高JTOL的同时降低恢复时钟抖动60%，该项成果发表在集成电路设计顶级会议VLSI 2021上。
3. 用于自供电传感器节点的极低电压极低功耗集成电路设计：2021年研制出一款0.15-1.6 GHz的极低电压极低功耗锁相环，首次将频率大于100MHz的锁相环的最低工作电压降低至0.25 V，且功耗首次降低至10 μW（@ 200 MHz）以下，能够较好满足自供电传感器节点SoC芯片的应用，该项成果发表在集成电路设计顶级期刊JSSC 2021 (IEEE Journal of Solid-State Circuits)上。
联系方式：
E-mail: zhangzhao11@semi.ac.cn
代表性论文或著作（*为通讯作者，#为共同第一作者）：
10篇代表性期刊论文：
1. Zhao Zhang*, Guang Zhu and C. Patrick Yue, “A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture with Dynamic Charge Pumps”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 6, 2021.
2. Zhao Zhang*, Guang Zhu, Can Wang, Li Wang, and C. Patrick Yue, “A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL Based Multiphase Clock Generator”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 10, 2020.
3. Zhao Zhang*, Guang Zhu and C. Patrick Yue, “A 0.65 V 12-to-16 GHz Sub-Sampling PLL with 56.4 fsrms Integrated Jitter and -256.4-dB FoM”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 6, 2020.
4. Junfeng Hu, Z. Zhang #, and Quan Pan, “A 15-Gb/s 0.0037-mm2 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator”, IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II), Vol. 67, No. 9, 2020.
5. Zhao Zhang*, “CMOS analog and mixed-signal phase-locked loops: An overview”, Journal of Semiconductors, Vol. 41, No. 11, 2020.
6. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu and Nanjian Wu, “An 18-to-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL with Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique”, IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), Vol. 66, No. 10, 2019.
7. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu and Nanjian Wu, “A 0.1-to-5 GHz Wideband ΔΣ Fractional-N Frequency Synthesizer for software-Defined Radio Application”, IET Circuit, Device & System, Vol. 13, No. 7, 2019.
8. Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu and Nanjian Wu, “A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 5, 2018.
9. Zhao Zhang, Liyuan Liu, Peng Feng, and Nanjian Wu, "A 2.4-to-3.6 GHz Wideband Subharmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 3, 2017.
10. Can Wang, Li Wang, Zhao Zhang et al., "A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects”, IEEE Open Journal of Circuits and Systems (IEEE OJCAS), Vol. 2, 2021.
10篇代表性会议论文：
1. Zhao Zhang, Guang Zhu and C. Patrick Yue, “A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM”, IEEE International Solid-State Circuit Conference (ISSCC 2019), Feb. 2019.
2. Zhao Zhang et al, “A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps”, 2019 Symposia on VLSI Circuits (VLSI 2019), Jun. 2019.
3. Zhao Zhang, Guang Zhu, Can Wang, Li Wang, and C. Patrick Yue, “A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator”, IEEE Asian Solid-State Circuit Conference (A-SSCC 2019), Nov. 2019.
4. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu and Nanjian Wu, “A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range”, IEEE Asian Solid-State Circuit Conference (A-SSCC 2018), Nov. 2018.
5. Zhao Zhang, Guang Zhu, and C. Patrick Yue, “A 2-to-10 GHz 1.4-mW 50% Duty-Cycle Corrector in 40-nm CMOS process”, 2018 International Conference on Electron Devices and Solid-State Circuits (EDSSC 2018) (Invited paper), Jun. 2018.
6. Zhao Zhang, Guang Zhu and C. Patrick Yue, “A 12.5-Gb/s 4.8-mW Full-Rate CDR with Low-Power Sample-and-Hold Linear Phase Detector”, 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2018), Nov. 2018.
7. Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu and Nanjian Wu, “A 18-to-23 GHz -253.5dB-FoM Sub-Harmonically Injection-Locked ADPLL with ILFD Aided Adaptive Injection Timing Alignment Technique”, IEEE Asian Solid-State Circuit Conference (A-SSCC 2017), Nov. 2017.
8. Zhao Zhang, Liyuan Liu, and Nanjian Wu, “A Novel 2.4-to-3.6 GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptively Aligned Injection Timing”, IEEE Asian Solid-State Circuit Conference (A-SSCC 2014), Nov. 2014.
9. Li Wang, Zhao Zhang, and C. Patrick Yue, “A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery”, 2021 Symposia on VLSI Circuits (VLSI 2021), Jun. 2021.
10. Can Wang, Guang Zhu, Zhao Zhang, and C. Patrick Yue, “A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects”, 2019 Symposia on VLSI Circuits (VLSI 2019), Jun. 2019.